The ICL 7502 -
Order Code (Instructions)_

The ICL 7502 had a very straightforward 16-bit instruction format, as befits a simple, word-orientated machine with a one-dimensional address space. The mill was register-symmetric and all registers (known as X0 to XF) could be used in all instructions, subject to certain limitations on store-indexing as described below. There was no ACCUMULATOR in the traditional sense, or special-purpose registers apart from XF which was the PROGRAMME COUNTER.

A rumour circulated at the time when I was at ICL that the instruction set of the 7502 was designed as a dissertation in computing by by the son of Ed Mack, who was Director of Product Development at that time. Since the 7502 features in no book of computing history that I have ever read I have no clue as to the truth of this rumour. If you know, please tell me.

The topmost 4 bits of the word indicated the instruction type, the tag IMMEDIATE indicates that the low byte of the instruction was an immediate operand:
  • 0 - MASK (immediate)
  • 1 - I/O and CONTROL
  • 2 - STORE READ/WRITE
  • 3 - SHIFT RIGHT
  • 4 - RELATIVE JUMP
  • 5 - BRANCH
  • 6 - LOAD (immediate)
  • 7 - COMPARE (immediate)
  • 8 - ADD (immediate)
  • 9 - AND (immediate)
  • A - DUMP/RECOVER SCRATCHPAD
  • B - MOVE BLOCK *
  • C - SEARCH BLOCK *
  • D - MODIFY BLOCK *
  • E - TRANSLATE BLOCK *
  • F - REGISTER ARITHMETIC
  • * - NOT STATE 4

Store-indexing instructions ran into a problem because there were not enough bits in an instruction to specify a target register, a store address register, an index register and a read/write direction bit. For this instruction the index register could only be one of the same four-register group (X0 to X3, X4 to X7 etc.). A modified version of the store instructions allowed a 2-bit literal offset to be used as a fixed index in place of another register.

Code for the interrupt-handling KERNEL system was developed at Kidsgrove, and written in an assembly language that exploited the CODE feature of the 1900 series CORAL66 compiler. A separate linker would knit together the code modules and create a memory image that could be TELELOADED to a waiting system.

Here is a snatch of code loaded at an arbitary store address (X0100) to write incrementing data characters from 20H to 6FH to video store (VDU 1 located at X4000), and recycling endlessly:

0100:6040LDI X0,40H; Set X0 to 40H
0101:3070SRC X0,8,X0; Rotate to high byte (X4000 for screen start)
0102:FF33XOR X3,X3; Clear X3 for index
0103:6120LDI X1,20H; First character (space)
0104:210BSTO X1,X0,X3; Store char(X1) at start(X0) + index(X3)
0105:8101ADDI X1,1; Bump character
0106:8301ADDI X3,1; Bump index
0107:7160SKNE X1,60H; Check for valid character limit
0108:4002JMP $+2; Jump to check end of screen
0109:4FFBJMP $-5; Jump to store write
010A:33B4SRA X3,4,X4; Divide index by 16 into X4
010B:7480SKNE X4,80H; Skip if not 128
010C:FF33XOR X3,X3; Reset index register
010D:4FF6JMP $-10; Jump to start character load